1. Field of the Invention
The present invention relates to semiconductor devices and fabrication of semiconductor devices, and more particularly, to damascene metal wiring pattern and methods for fabricating damascene metal wiring.
2. Description of the Related Art
Recent semiconductor device manufacturing technology uses copper (Cu) as a wiring material in semiconductor devices having small feature sizes because copper has low resistivity and high resistance to electro-migration. However, copper""s complicated chemical reactions makes copper difficult to pattern and use for metal wiring. For example, copper wiring patterns are easily oxidized when exposed to air. Such oxidation increases the resistance of the wiring pattern. Thus, to prevent oxidation, damascene wiring is frequently used when forming copper wiring patterns.
The process for forming damascene wiring forms and patterns an insulative layer to create damascene regions or depressions in the insulative layer. Next, a conductive material such as copper is deposited on the insulative layer, filling the damascene regions. Then, chemical mechanical polishing (CMP) or an etch-back process planarizes the conductive layer to expose the insulative layer. As a result, a damascene metal wiring pattern is left in the damascene regions. However, the planarization by CMP can result in dishing or erosion of the damascene metal wiring pattern.
FIG. 1 is a cross-sectional view of a semiconductor device including dished metal wiring. In FIG. 1, an insulative layer pattern 110 overlies a semiconductor substrate 100, and damascene metal wiring 130 is formed in insulative layer pattern 110 by the method described above. A barrier layer 120 is between damascene metal wiring pattern 130 and insulative layer pattern 110. Region xe2x80x98axe2x80x99 shows dishing of a portion of damascene metal wiring pattern 130. Dishing occurs because of the faster polishing rate at the center of metal wiring pattern 130 relative to polishing rate at the perimeter of metal wiring pattern 130. Thus, dishing is more severe when metal wiring pattern 130 is wider.
FIG. 2 is a cross-sectional view of a portion of a semiconductor device where Damascene metal wiring pattern 130 has an eroded surface. Here, region b of FIG. 2 corresponds to the eroded portion of Darnascene metal wiring pattern 130. Erosion arises from CMP during Damascene processing and occurs where there is insufficient oxide area to act as a CMP stop during the CMP planarization. The CMP process has a higher polishing rate where the percentage area of metal is higher. Accordingly, CMP can erode oxide 110 and Damascene metal wiring pattern 130 in areas. such as region b. In particular, an area including closely packed regions of metal wiring pattern 130 separated by narrow portions of insulative layer pattern 110 is susceptible to the erosion.
The dishing or erosion thins the metal wiring and thus increases the sheet resistance of the metal wiring. Further, the increase in sheet resistance is not constant. The sheet resistance may increase by tens of percentage points depending on the circumstances and the layout of the metal wiring. The high or inconsistent resistance makes the operation of a semiconductor device difficult or lowers the reliability of a semiconductor device, especially of a high power semiconductor device. In the case of analog devices that demand accurate and constant resistance of the wiring patterns, the design rules for the damasecene metal wiring pattern are considerably restricted to prevent the dishing or erosion of the damascene metal wiring pattern.
In accordance with an aspect of the invention, device fabrication process forms a dummy layer over portions of conductive layer before a CMP process. The dummy layer slows the removal of material from the covered portions of the conductive layer and thereby prevents overpolishing that could otherwise cause dishing or erosion in a Damascene wiring pattern. The dummy layers are typically removed completely when forming damascene wiring, but in some embodiment, portions of the dummy layer remain in the finished semiconductor devices.
A method according to one embodiment of the invention includes: forming an insulative layer on a semiconductor substrate; patterning the insulative layer to form a damascene region in the insulative layer; forming a conductive layer on the insulative layer, filling the damascene region; forming a dummy layer on a portion of the conductive layer that is in the damascene region of the insulative layer; and planarizing the semiconductor substrate by removing portions of the dummy layer and the conductive layer until the insulative layer is exposed. The pattern of the dummy layer is such that the dummy layer is above the wide damascene region, e.g., damascene regions that are 10 xcexcm or more wide.
Chemical mechanical polishing (CMP) planarizes the semiconductor structure. The CMP is less selective to the dummy layer than to the conductive layer. For example, the relative selectivity between the conductive layer and dummy layer is preferably 5 to 1. In exemplary embodiments, the dummy layer is a SiO2, Si3N4, TiO2, or TiN layer, having the thickness between about 500 xc3x85 and 5000 xc3x85.
In another method, the patterning of the insulative layer can form a number of damascene regions that are closely spaced. In this case, the dummy layer is formed on a portion of the conductive layer, under which the damascene regions occupy 20% or more of the area of the insulative layer. For protection of these areas during CMP, the selectivity of the dummy layer is the same as or lower than that of the conductive layer, preferably between 1:1 and 1:2. The thickness of the dummy layer is between 500 xc3x85 and 3000 xc3x85.
The method can further include forming a second conductive layer on the dummy layer and conductive layer after forming the dummy layer. In this case, the top surface of the portion of the conductive layer below the dummy layer may be lower than the top surface of the insulative layer, preferably by 500 xc3x85 to 1000 xc3x85 so that part of the dummy layer remains after CMP planarization.
In accordance with the present invention, still another method of forming a conductive pattern of a semiconductor device includes: forming an insulative layer; patterning the insulative layer to form a plurality of damascene regions in the insulative layer; forming a conductive layer that fills the damascene regions; forming a first dummy layer on portions of the conductive layer over wide damascene regions; forming a second dummy layer on portions of the conductive layer over closely packed damascene regions; and planarizing the semiconductor substrate by removing portions of the dummy layers and the conductive layer until the insulative layer is exposed. This method combines features of the two methods described above.
Another aspect of the present invention provides a semiconductor device comprising: an insulative layer in which a damascene region is formed; a conductive layer which fills the damascene region; and a dummy layer overlying the conductive layer. The semiconductor device can further include a barrier layer between the conductive layer and the insulative layer.
In accordance with another embodiment of the present invention, a semiconductor device includes an insulative layer overlying a conductive layer or lower wiring layer. The insulative layer includes a damascene region and a via hole, and the via hole exposes the conductive layer through the damascene region. A second conductive layer fills the damascene region and the via hole, and a dummy layer overlies the damascene region.